ET-SoC-1 Chip Diagram (et-soc1-chip-diagram & et-soc1-in-3d): 103-Node Geometry, Viewport, Parameter & 2D↔3D Bridge Audit

Written 2026-10-14 (Wednesday, week 42) on the Intel (Intel-mbp) from ~/git0/aifoundry (Antigravity session 76c9e0d8-e767-4f1a-9bd1-f47e38e1661b). Audited live snapshots et-soc1-chip-diagram (c753607a8c79, space 6cfdea5c-a598-438e-bd1a-613093ede523) and et-soc1-in-3d (7f69884894ba, space 9018f695-7165-4852-9fbb-4f49cfcaefa1), documented in Discussion #3 (#3 + #3.1) on the diagram space, with two standalone interactive mockup spaces deployed.

Interactive Mockups & Artifacts

1. ET-SoC-1 Diagram Mockup: Unified 2D ↔ 3D Bridge & N7 Material Palette (tailnet, UUID 8db86484-8a76-471f-baf1-8e2e4586f8b3, SHA 61c162042559) — Interactive side-by-side 2D cross-section and 3D isometric FinFET/channel bridge comparing the current disconnected palettes (#bb9654 gold / #526e91 slate / #41d7ba teal) against the unified --c1..--c5 paper palette with TSMC N7 dimensions (57 nm CPP, 30 nm fin pitch, 6 × 52 nm fin, 16.5 nm channel, 0.517 V minion rail, ~75 e⁻ vs ~0.005 e⁻), plus an interactive simulator and code patch for context-preserving 2D↔3D navigation (lib.wire support, SEL._kid awareness, and ?from= branch preservation).
2. ET-SoC-1 Diagram Mockup: Multi-Level Stylistic, Geometry & Prose Refinements (tailnet, UUID 9f19b633-e194-4a68-9b15-b85828b2ac67, SHA ba216b723c6a) — Interactive before/after SVG verifier for the 9 desktop header-title vs. epistemic-tag-pill collisions, the phone viewport (PH = true) right-edge clipping on st29 and package, the 5 unprotected +k parameter parsers (NaN title bug), and the 3 internal prose/metadata contradictions.

Executive Summary of Verified Findings

By executing the full JavaScript rendering engine of index.html (10,642 lines) and ladder-data.json (813 lazy facts + 304 core facts = 1,117 facts, 0 missing fact references) across all 103 registered NODES in both desktop (PH = false) and phone (PH = true) viewports (work/chip-diagram-deep-audit/node_audit.js and header_and_wire_audit.js), we identified five concrete classes of bugs and stylistic inconsistencies:

1. Desktop Header Title vs. Epistemic Tag Pill Collisions across 9 Inner Scales (KT.frame L4365–4373 & ihead L6226–6228)

On desktop (!PH), KT.frame and ihead draw the 30px bold title (.t-big / .i-t, starting at x = -150, y = -32) on the exact same vertical band (y = -56..-30) as the right-aligned epistemic tag pills (xr = 1074 moving left), without wrapping or checking available width. When a scale uses GT = [['generic', 'textbook construction'], ['unknown', 'this chip’s own circuit: not published']] (L6842, which spans 614 SVG units from x = 460..1074) or has a 50+ character title, the title and pill collide:

• Fix: Shorten GT[1][1] from 'this chip’s own circuit: not published' to 'chip circuit: not published' (freeing 103 SVG units across all 14 GT scales) and step down the title font size when titleRight > tagLeft - 18.

2. Phone Mode (PH = true) Viewport Clipping & Crowding (st29 L3980, package L4243, otitle L3586)

• st29 (29th Street, L3980): T(L, X0 + W + 10, Y0 + 6, 'sea level', 'o-s') places 'sea level' at x = 890..994 (text-anchor="start"), whereas the phone viewport opv() (L3557) is x = 130..890 (w = 760). Thus 'sea level' is 100% clipped off the right edge on phones. Contrast Bernal Heights' summit four lines below (L3984), which uses 'end' at X0 + W = 880.
• package (The package, L4243): T(gs, sx, sy - 12, 'in section, heights ×5 (3.9 mm in all; layer heights generic)', 'o-s') uses raw T(...) instead of owrap(...). On phone (o-s = 24px), this 61-character line spans x = 150..882 right to the viewport border, while at y = 690 sbar(L, 150, 690, ...) shares the bottom row with otitle's bottom-right tag pill (y = 690..728).
• Fix: On PH, anchor 'sea level' with 'end' at X0 + W, Y0 - 10 and wrap the package section heading via owrap(gs, sx, PH ? sy - 38 : sy - 12, ..., 710, 'o-s').

3. Unprotected +k Parameter Parsing (NaN Title Bug on 5 Parameterized Scales)

While shire.bank, shire.subbank, shire.panel, memshire, dram, and dram.bank wrap their parameter in n0 = v => (v == null || isNaN(v) ? 0 : v) (L5759) so bare hashes like #at=shire.bank safely default to 0, five scales use raw +k: - shire (L3521: parse: k => ({sid: +k})) → "Shire NaN: thirty-two cores…" - l1d.block (L5775: parse: k => ({block: +k})) → "Block NaN of the L1 data scratchpad" - shire.neigh (L5971: parse: k => ({nb: +k})) → "Neighborhood NaN of shire 0…" - vpu.lane (L5984: parse: k => ({lane: +k})) → "Lane NaN of the vector unit" - pcie.lane (L7218: parse: k => ({lane: +k})) → "PCIe lane NaN: a SerDes, block by block" - Fix: Wrap +k in n0(+k) on all five scales.

4. 2D ↔ 3D Companion Bridge & Material Palette Alignment (index.html L7659–7664 ↔ et-soc1-in-3d)

• Loss of user's ladder branch on return: Users reach lib.finfet, lib.fin, and lib.channel from compute (.../vpu.lane.fma/.../lib.xor/lib.finfet), SRAM (.../lib.sram6t/lib.finfet), or mesh (.../mesh.link.wire/lib.inverter/lib.finfet) branches, but clicking "← Back to the chip diagram" in et-soc1-in-3d hardcodes #at=die.metal/lib.finfet..., ripping the user out of their compute/SRAM/mesh branch and teleporting them into the die.metal branch. Passing ?from=${encodeURIComponent(pathHash())} preserves the exact ladder path.
• Missing lib.wire 3D link (L7659): view3d lists 'die.metal', 'lib.finfet', 'lib.fin', 'lib.channel', but omits 'lib.wire' ("Copper wiring, in section"), even though et-soc1-in-3d#metal specifically features "SECTION / A COPPER CONNECTION (Copper · Liner · Dielectric · Vertical via)".
• Selected-part mismatch in panel(html) (L7659): panel() checks only cur.id (Z.path[Z.path.length - 1].id) and ignores SEL._kid. Clicking "The fins" (kid: lib.fin) while on lib.finfet opens #finfet instead of #fin; clicking "One transistor" (kid: lib.finfet) on lib.xor or lib.sram6t renders no 3D link at all.
• Palette & N7 numbers: Harmonizing et-soc1-in-3d with --c1 (#2a78d6 metal gate), --c3 (#1baf7a silicon fin), --c2 (#eb6834 channel/electrons), --c4 (#d49b1f HfO₂), and --c5 (#8854d0 Co/Cu) and surfacing the 2D diagram's TSMC N7 / ET-SoC-1 metrics (57 nm CPP, 30 nm fin pitch, 6 × 52 nm fin, 16.5 nm channel, 0.517 V minion rail) makes the 2D→3D jump visually seamless.

5. Internal Prose & Metadata Contradictions

• COMPS.inferred (L7768): Clicking inferred · what would settle it › on the die still says "Still inferred: the LPDDR4X pairing (dashed), the die's east-west handedness, the routes' turning order, the inside of a shire, and the sizes." — contradicting L993 (byline), L9513 (Tour step 3), L10098 (#honest-text: "Routes are measured now (L104, 29 September)"), and ASKS (where the routes ask is settled: true).
• COMPS.mesh (L7711): Says "Routes are shortest paths in dimension order, measured on two cards on 29 September", whereas L993, L1153, L10098, and D.facts['L104'].cards (["a2", "a3", "a1c1"]) all state three cards.
• Space description metadata (get_space): The spacesheep space description still reads "six data flows to memory with measured latency, bandwidth and energy; a 12-step tour", whereas the live diagram has eleven data flows and a 17-step tour.